1. Field
Exemplary embodiments of the present invention relate to a memory, a memory system and a method for operating the memory.
2. Description of the Related Art
A memory cell of a memory comprises a transistor for serving as a switch and a capacitor for storing charge (data). Data is identified as HIGH (logic 1) or Low (logic 0) depending on whether or not data is stored in the capacitor, that is, whether voltage level of the capacitor is high or low.
Ideally, there is no power consumption in retaining data in the memory cell because data is stored in the form of accumulation of charge in the memory cell. However, there is a leakage current due to PN junction of a MOS transistor, which leads to loss of charge accumulated in the capacitor and loss of data stored in the memory cell. To prevent the loss of data, the memory cell may be recharged by reading its data before the data is lost. Such an operation of reading and recharging is to be performed repeatedly for secure data storage of the memory cell. The operation is referred to as a refresh operation.
The refresh operation may be performed in response to a refresh command inputted from a memory controller to the memory. The memory controller generates the refresh command every predetermined time in consideration of data retention time of the memory. For example, the memory controller generates 8,000 refresh commands for 64 ms when the data retention time is 64 ms and all of the memory cells in the memory are refreshed with 8,000 refresh commands.
A space between word lines is getting shorter and coupling effect between adjacent word lines is becoming a concern as degree of memory integration is getting higher. Therefore, when a specific word line in the memory is activated frequently or too many times for the refresh operations, data of a memory cell connected to a word line adjacent to the specific word line may be damaged.
FIG. 1 is a diagram of a part of a cell array in a memory illustrating word line disturbance effect. Referring to FIG. 1, the cell array may include bit lines BL and 3 word lines WLK−1, WLK, and WLK+1 disposed adjacently.
The word line WLK marked with HIGH_ACT is activated with high frequency. The word lines WLK−1 and WLK+1 are adjacent to the word line WLK. Memory cells CELL_K−1, CELL_K and CELLK+1 are connected to the word lines WLK−1, WLK and WLK+1, respectively. The memory cells CELL_K−1, CELL_K and CELL_K+1 comprise cell transistors TR_K−1, TR_K and TR_K+1 and cell capacitors CAP_K−1, CAP_K and CAP_K+1, respectively.
When the word line WLK is activated or precharged (deactivated), voltage levels of the word lines WLK−1 and WLK+1 rise or fall and charge stored in the cell capacitors CAP_K−1 and CAP_K+1 of the word lines WLK−1 and WLK+1 is affected due to coupling effects between the word lines WLK−1 and WLK and between the word lines WLK and WLK+1. Change in the charge stored in the cell capacitors CAP_K−1 and CAP_K+1 of the word lines WLK−1 and WLK+1 may cause loss of data stored therein when the voltage level of the word line WLK toggles frequently between the activated state and the precharged state as the word line WLK is activated and precharged frequently.
As the voltage level of the word line WLK toggles between the activated state and the precharged state, electro-magnetic wave may be generated to bring about inflow or outflow of electron to or from the cell capacitors CAP_K−1 and CAP_K+1 of the adjacent word lines WLK−1 and WLK+1. Therefore, the data stored in the memory cell may be damaged.